FIG. 5 shows a block diagram of a conventional flash memory card 500 and an information processing appliance 501 (which is referred to as a host hereinafter). The flash memory card 500 is connected with the host 501 through, for example, five different times of clients or busses, a data line or a data bus 502, a clock line 503, a power line 504, which provides the power supply voltage VDD, a ground line 505 providing a second reference potential, usually the ground potential VSS, and a command line 506, which is used to transfer commands from the host 501 to the flash memory card 500.
A host interface 507 of the flash memory card 500 receives commands from the host 501 through the command line 506 and decodes the received commands. When the command is a write command, for example, the host interface 507 decodes the command into a logical address 508 provided by the host 501 as the writing destination of data and sends the logical address 508 to a flash memory controller 509 of the flash memory card 500. Furthermore, the host interface 507 receives data objects 510 to be written from the data line 502 and stores the data objects 510 in a data buffer 511.
In the flash memory controller 509, an address conversion section (not shown) is fed from the host interface 501 with the logical address 508 showing the writing destination of the data object 510. The address conversion section brings the physical addresses of generally more than one area into correspondence with one logical address. Here, one area is equivalent to, for example, two pages inside a non-volatile memory cell array 512 comprising a multiplicity of non-volatile memory cells of the flash memory 513. In particular, the pages belonging to the same area each belong to separate physical blocks. The non-volatile flash memory cell array 512 is generally divided into more than one page each having a fixed number of memory cells, and further divided into more than one physical block each having a fixed number of pages. Each of the memory cells can take two states, “1” and “0”. Thereby, one of the memory cells can store 1-bit data therein, in the following also referred to as data item.
The address conversion section, when fed with the logical address 508, showing the writing destination of the data object 510, selects a free blank area in the memory cell array 512 and assigns the write target area of the data object 510 to the respective free area. The address conversion section further brings the physical address 514 of this area in correspondence with the above-mentioned logical address 508.
A write section (not shown) sends the physical address 514 of the write target area to an address decoder 515 of the flash memory 513. In conjunction with that, the write section sends the data object 510 to be written from the data buffer 511 to a page buffer 516 of the flash memory 513.
The flash memory 513 comprises, for example, two page buffers 516. Each of the page buffers 516 can store one-page data. In other words, the two page buffers 516 can store one-area data in total. Accordingly, the data objects 510 to be written, in the following also denoted as data words, which are sent out from the data buffer 511, are stored in the page buffers 516 on an area-by-area basis. The one-area data items, i.e., the data words, stored in the two page buffers 516 are written in parallel onto the two pages designated by the address decoder 515. Thus, the conventional flash memory card 500 performs the data writing into the flash memory 513 in the two physical blocks in parallel, thereby shortening the writing duration, wherein data words of a predefined fixed length are used, usually using a data word of 128 bits length.
The flash memory card 500 brings the physical address of the area in which the new data is to be written, into correspondence with the logical address showing the writing destination. In addition, in the flash memory, data items are erased only collectively in each of the physical blocks mentioned above.
In some common flash memory cells, only a predetermined maximum number of flash memory cells can be programmed with using one programming pulse due to the current needed for changing the state of a flash memory cell, which is usually implemented by means of a floating gate transistor or a charge trapping layer transistor.
In a common flash memory card 500, no overwriting of an already programmed flash memory cell is possible. Usually, before writing new data in a physical block, which has already been programmed, the physical block is firstly erased and then, after the erased process has been finished, the new data is programmed into this physical block.
The erase process is performed by means of an erasing circuit 517, which is coupled to the read section and is provided with the physical address and with the non-volatile memory cell array 512 and the address decoder 515.
Since usually, a flash memory card 500 is used in a portable information processing appliance, such as a notebook computer, a personal digital assistant (PDA), or/and a digital camera, and records large quantities of digital data such as image data in the internal recording media, there is need to improve the memory device architecture and corresponding method for programming a non-volatile memory cell array in order to save the required energy for programming. Furthermore, the programming speed is also needed to be increased in order to improve the usability of the device.